In electronic design automation, simulators are used to autonomously interpret a system specification (e.g., a logic design model), and to simulate the behavior of the system over a simulated period of time. The system may be specified at various levels of detail and may include various elements. For example, a specification for a digital electronic circuit may be described at an algorithm level, at a register-transfer-level (RTL), or at a gate level.
An algorithm level specification describes the relationship between a set of inputs to a set of outputs using a set of computations. At a more detailed register transfer level, the system is described in terms of interconnected combinatorial logic blocks and registers (memory storage devices). At an even more detailed gate-level description level, the system may be described in terms of physical transistors.
As the level of detail increases, simulation of the system requires a more detailed treatment of the propagation of information through the system over time. For example, in RTL logic, the behavior of the circuit involves a time sequence of periodic data transfers, from register to register, through combinatorial blocks which transform the data according to logical rules.
The level of detail required in the simulation depends on the purpose of the simulation. For example, to determine if the circuit is logically correct, assumptions can be made to simplify the simulation. In a RTL design for example, the data transfers from register to register may be assumed to occur simultaneously on a periodic basis (e.g., on clock cycles) and the transformation and propagation of the data through the combinatorial blocks may be assumed to occur instantaneously (e.g., with zero delay). This is the approach taken by a class of simulators called cycle-based simulators. While cycle based simulators are useful for initial logic design and are fast, they are inherently inaccurate and can lead to undetected race conditions and glitches which otherwise would have been caught by simulators that take into account propagation delays and real world factors such as clock skew. A designer using a cycle based simulator has to ensure that designs are cycle accurate and loss of this information will not affect their verification results.
At the other end of the spectrum, a class of analog circuit simulators, such as SPICE, may be used to determine precise circuit behavior by calculating the state of every signal at every step in a sequence of time instances. However, analog type simulators require a prohibitive amount of computation to be useful in simulating most digital systems.
In between cycle based simulators and analog simulators, are a class of simulators called event-driven simulators, which model the propagation of data between and through design elements as a sequence of events having non-zero delays. In contrast to a cycle based simulator, an event-driven simulator permits a designer to examine the propagation of data within a single clock cycle. However, unlike analog simulators, event-driven simulators do not model every iteration of time, but calculate data only at events (e.g., at changes in the state of the system).
To perform event-driven simulation, a concept of a delta delay is introduced. A delta delay is an infinitesimally small advance in time that is simulated to have occurred for each event. The delta delays allows events to be ordered in sequence in a deterministic way that preserves the causal effect of an event occurring at one instant in time (e.g., the input to a logic gate changing) to another event occurring at a later instant in time (e.g., the output of the logic gate changing). For example, in a RTL design, within the simulation of one clock cycle, a signal at the input of a combinatorial block may change causing an event. This event may cause a subsequent event on the output of the combinatorial block, which may cause a subsequent event at the input of another combinatorial block connected downstream to the first combinatorial block, and so on. As events are simulated, more events may be created. The event-driven simulator handles these events by building an event queue which evaluates each event in the order they occur. Because each event in the queue occurs in a simulated delta delay, events are simulated in delta time cycles which reflect the order in which events occur, but which do not advance the simulated time cycle.
While event-driven simulation is much more efficient than full analog simulation, the more delta cycles that are created during simulation, the longer the simulation takes to run. For many designs, event-driven simulation can still be time prohibitive. However, it is often the case in these designs that the designer is only concerned with observing accurate simulation of a limited number of signals, like primary outputs and inputs or elements within the design. For these cases, it is desirable to reduce the complexity of the simulation, while maintaining the delta-accurate event based simulation of the limited number of desired signals and elements.